Platform ASICs are designed for quick development with minimal test cost. Development and test costs make insurance that yield and reliability goals are met elusive. In particular, goals for testing defect mechanisms that result in timing delays within the circuit are difficult to achieve.
Conventional functional and conventional scan type tests at high speeds are implemented to monitor fabrication excursions that would affect chip speed. The cost of implementing high speed tests is prohibitive for a platform ASIC environment where minimal test cost is desired.